System for generating whole and composite patterns for a display device

ABSTRACT

A pattern generating system for use with a display device including a matrix electrode assembly comprises a plurality of pattern signal generators for displaying different patterns on the matrix electrode assembly. Means is provided to selectively drive one of the plurality of pattern signal generators for displaying a selected one of the patterns or simultaneously driving a plurality of pattern signal generators for displaying modified patterns on the matrix electrode assembly by synthesizing different patterns. Alternatively, a partial pattern signal generator is added which is driven concurrently with one of the plurality of pattern signal generators for displaying a modified pattern.

United States Patent [1 1 Naka [ SYSTEM FOR GENERATING WHOLE AND COMPOSITE PATTERNS FOR A DISPLAY DEVICE [75] Inventor: Katsushi Naka, lse City, Mie

Prefecture, Japan [73] Assignee: Ise Electronics Corporation, lse

City, Japan [22] Filed: Sept. 3, 1971 [21] Appl. No.: 177,635

[30] Foreign Application Priority Data Sept. 7, 1970 Japan 45/77946 [52] U.S. Cl. 340/324 AD, 340/336, 178/30 [51] Int. Cl. G06f 3/14 [58] Field of Search 340/324 A, 336; 178/30 [56] References Cited UNITED STATES PATENTS 3,331,985 7/1967 l-lammann 340/336 12/1966 Rychlewski 340/336 Primary Examiner-John W. Caldwell Assistant ExaminerMarshall M. Curtis Att0rneyChittick, Pfund, Birch, Samuels & Gauthier [57] ABSTRACT A pattern generating system for use with a display device including a matrix electrode assembly comprises a plurality of pattern signal generators for displaying different patterns on the matrix electrode assembly. Means is provided to selectively drive one of the plurality of pattern signal generators for displaying a selected one of the patterns or simultaneously driving a plurality of pattern signal generators for displaying modified patterns on the matrix electrode assembly by synthesizing different patterns. Alternatively, a partial pattern signal generator is added which is driven concurrently with one of the plurality of pattern signal generators for displaying a modified pattern.

2 Claims, 9 Drawing Figures PATENIEBoma ma 3,768,091

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INVENTOR KATSUS HI I NAKA v ATTORNEY PATENTEDUEI 23 I975 SHEET 0F 4 ATTORNEY SYSTEM FOR GENERATING WHOLE AND COMPOSITE PATTERNS FOR A DISPLAY DEVICE BACKGROUND OF THE INVENTION This invention relates to a pattern generating system for a pattern display device including a matrix electrode assembly. I

FIG. 1 of the accompanying drawing illustrates one example of a pattern display device including a matrix electrode assembly. The pattern display device comprises a glass envelope 1, a fluorescent screen 2 formed on the inner surface of the face plate of the glass envelope, a cathode 3, and a matrix electrode assembly 4 consisting of a plurality of X-axis electrodes 5, a plurality of Y-axis electrodes 6 disposed at right angles with respect to the X-axis electodes, anda shield plate 7 interposed between X and Y-axis electrodes and 6. The

shield plate 7 is formed with a plurality of perforations (not shown) at the crossing points of the X and Y-axis electrodes which are also provided with perforations at the crossing points. There are further provided an acceleration electrode 8 which functions to accelerate electron beams that have passed through the perforations of the shield plate and' a deflection coil 9 mounted on the neck of the glass envelope.

The electron beam emitted from cathode electrode 3 is divided into a plurality of, for example 35, electron beams by the matrix electrode assembly 4. As is well known in the art,.positive potential is applied to a selectedone of the X-axis electrodes 5 and a selected one of the Y-axis electrodes 6 so that only the perforations corresponding'tothe crossing points of these selected electrodes permit the passage of the electron beam. In other words, only said perforations are selected. The electron beam that has passed through these selected perforations is accelerated by the acceleration electrode 8 and is then deflected by deflection coil 9 to impinge upon the fluorescent screen 2'th'us causing it to luminesce. In thismanner, it is possible to display a desired pattern on the fluorescent screen'2as a combination of dots by selecting-X andY-axis electrodes corresponding to the pattern desired to be displayed.

F IG. 2 shows a typicalpattern signal generating circuit and a matrix electrode assembly selectively driven thereby. The pattern signal generating circuit comprises input terminals 11 to 15 which receive clock signals, diodes l6 to'32 which are connected across conductors 33-to 37 connected to input terminals 11 to 15, respectively and conductors 38 to 44. The matrix elec trode assembly comprises a plurality of X-axis electrodes 5a to 53', a plurality of Y-axis electrodes 6a to 6e and a shield plate 7 which is provided with aligned perforations 10 at each crossing point of a pair of Xand Y-axis electrodes. The X-axis electrodes 5a to 5g are connected to conductors 38; to 44, respectively whereas the Y-axis electrodes 6a to 6e to conductors celerated and deflected, these electron beams impinge upon the fluorescent screen 2 to cause it to luminesce. In operation, the clock pulses are applied sequentially to Y-axis elctrodes 6a to 6e so that perforations 10 are selected thereby displaying the pattern for each one of the Y-axis electrodes. At the same time by selecting one of the X-axis electrodes it is possible to display a letter H as shown in FIG. 4. Each pattern is displayed during an interval from T1 to T6 shown in FIG. 3. In this manner, by impressing upon the deflection coil 9 (FIG.1) a voltage having a waveform as shown in FIG. 3f, the position of displaying the pattern can be shifted in accordance with this waveform. 9

FIG. 5 illustrates another example of a prior art pattern signal generating circuit including input terminals to which clock pulses shown in FIGS. 3a to 3e are applied sequentially. Conductors 55 to 59 are connected to input terminals to 54 respectively. The opposite ends of these conductors are connected to corresponding Y-axis electrodes of the matrix electrode assembly, not shown. There are provided a plurality of AND gate cirucits 60 to 69 with one of their input terminals connected to conductors 55 to 59 respectively. The other input terminals of the AND gate circuits 60 to 64 are connected to a common selection terminal 70. In the same meanner, the other input terminals of AND gate circuits 65 to 69 are connected to another common selection terminal 71. OR gate circuits 72 to 85 are provided. Input terminals of OR gate circuits 72 to 78 are connected to the outputs of AND gate circuits 60 to 64,

respectively, and the outputs of these OR gate circuits are connected to conductors 86 to 92, respectively. On the other hand, the input terminals'of OR gate circuits 79 to 85 are connected to the outputs of AND gate circuits65 to 69, respectively, and the output terminals of these OR gate circuits are also connected to conductors 86 to 92, respective X-axis electrodes of the matrix electrode assembly.

In operation, clock pulses are sequentially impressed 0 upon input terminals 50 to 54 concurrently with the application of a selection signal upon the selection termi nal 70, thus sequentially producing outputs on the output terminals of the AND gate circuits 60 to 64. The ouput from AND gate circuit 60 is supplied to the input terminals of OR gate circuits 72 and 78. The output from AND gate circuit 61 is supplied 'to the inputterminals of OR gate circuits 72, 75 and 78, whereas the output from AND gate circuit 62 is supplied to the input terminals of OR gate circuits 72, 75 and 78. In the same manner, the output from AND gate circuit 63 is supplied to the input terminals of OR gate circuit72, 75 and 78 andthat of the AND gate circuit 64 to the input terminals of OR gate circuits 72, 73, 74, 75, 76, 77 and 78. Consequently, the output from AND gate circuit 60 selects perforations 1e and 72, shown in FIG. 7a of the matrix electrode assembly. The output from AND gate circuit 61 selects perforations 1d, 4d and 7d, shown-in FIG. 7b, and the output from AND gate circuit 62 selects perforations '10, 4c, and shown in FIG. 7a. In

thesa'me manner, the output from AND gate circuit 63 selects perforations lb, 4b and 7b shown in FIG. 7a, and that of the AND gate circuit 64 selects perforations 1a, 2a, 3a, 4a, 5a, 6a and 7a shown in FIG. 7a. Thus, the outputs from AND gate circuits60 to 64 select perforations shown as black dots in FIG. 7a whereby a letter E is constructed. In the same manner, concurrent applicationof the clock pulses upon input terminals 50 to 54 and a selectionsignal upon the selection terminal 71 results in the application of the outputs from AND gate circuits 65 to 69 upon input terminals of OR gate circuits 79 to 85 whereby perforations shown in FIG. 7b are selected to display a letter F.

With the pattern signal generating circuit constructed as above described, since various dots for constituting respective patterns are selected by the OR gate circuits, the number of gate circuits or component parts thereof increases with the number of patterns to be displayed. This not only complicates the circuit construction but also increases the chance of fault.

SUMMARY OF THE INVENTION It is therefore an object of this invention to provide an improved pattern generating system which can eliminate the defects described above and can be fabricated with a smaller number of component parts.

According to one aspect of this invention there is provided a pattern generating system for displaying patterns such as letters or digits on a display device including a matrix electrode assembly comprising a plurality of whole pattern signal generators for displaying different whole patterns on the matrix electrode assembly, a partial pattern signal generator, means for independently driving the whole pattern signal generators for displaying selected ones of the whole patterns and means for simultaneously driving selected ones of the plurality of whole pattern signal generators and the partial patterns generator to display a modified pattern on the matrix electrode assembly.

According to another aspect of the invention there is provided a pattern generating system for displaying patterns on a display device including a matrix electrode assembly, comprising a plurality of whole pattern signal generators for displaying whole different patterns on the matrix electrode assembly, means for driving a selected one of the plurality of whole pattern signal generators for displaying a selected pattern and means for simultaneously driving a certain plurality of whole pattern signal generators for displaying a modified pattern on the matrix electrode assembly by sythesizing whole different patterns.

BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawing:

FIG. 1 is a schematic representation of one example of a pattern display device;

FIG. 2 is a diagram to illustrate the basic construction of a prior art pattern generating system;

FIG. 3 shows waveforms helpful to understand the operation of the pattern generating system shown in FIG. 2;

FIG. 4 shows an example of a pattern displayed by the pattern generating system shown in FIG. 2;

FIG. 5 is a diagram to show a detailed connection of prior art pattern generating system;

FIG. 6 shows one example of the improved pattern generating system embodying the invention;

FIGS. 7a and 7b show examples of patterns formed by the circuits shown in FIGS. 5 and 6, and

FIG. 8 show other examples of the patterns that can be displayed.

DISCRIPTION OF THE PREFERRED EMBODIMENT FIG. 6 shows a connection diagram of one embodiment of the novel pattern generating system wherein component parts corresponding to those shown in FIG. 5 are designated by the same reference numerals. As shown in FIG. 6, there are provided a plurality of OR gate circuits 93 to 106. The input terminals of OR gate circuit 93 are connected to the output terminals of AND gate circuits 64 and 69 while the input terminals of OR gate circuit 94 are connected to the output terminals of AND gate circuits of 61, 62, 63, 66, 67, and 68. The input terminal of OR gate circuit 95 is connected to the output terminal of AND gate circuit 60 while the output terminal of OR gate circuit 95 is connected to conductor 86. The input terminals of OR gate circuit 96 are connected to the ouput terminals of respective AND gate circuits 60 to 63 and the output terminal of this OR gate circuit is connected to conductor 92. The input terminal of OR gate circuit 97 is connected to the output terminal of AND gate circuit 65 while the output terminal of this OR gate circuit is connected to conductor 86. The input terminals of OR gate circuits 98 to 104 are commonly connected to the output terminal of OR gate circuit 93 and the output terminals of OR gate circuits 98 to 104 are connected to conductors 86 to 92, respectively. Further, the input terminals of OR gate circuits 105 and 106 are commonly connected to the output terminal of OR gate circuit 94 whereas the output terminals of OR gate circuits 105 and 106 are'connected to conductors 86 and 89.

In operation, when clock pulse signals shown in FIGS. 3a to 32 are applied to input terminals 50 to 54 and when a selection signal is impressed upon the selection terminal 71, AND gate circuits 65 to 69 will produce outputs on their output terminals. Consequently, in the same manner as has been described in connection with FIG. 5, the output from AND gate circuit 65 selects a perforation 1e shown in FIG. 7b via OR gate circuit 97 while the output from AND gate circuit 66 selects perforations 1d and 4d shown in FIG. 7b via OR gate circuits 94, 105 and 106. In the same manner, the output from AND gate circuit 67 selects perforations 1c and 4c via OR gate circuits 94, 105 and 106 and the output of AND gate circuit 68 selects perforations lb and 4b shown in FIG. 7b via OR gate circuits 94, 105 and 106. Further, AND gate circuit 69 selects perforations 1a, 2a, 3a, 4a, 5a, 6a and 7a via OR gate circuits 93 and 98 to 104. Consequently, the component elements bounded by dotted lines 107 cooperate to produce signal for a pattern F as shown in FIG. 7b. When clock pulses are sequentially applied upon terminals 50 and 54 concurrently with the application of a selection signal upon selection terminal 70, AND gate circuits 60 to 64 sequentially provide outputs. Under these circumstances since the output terminals of AND gate circuits 61 to 64 are respectively connected to OR gate circuits 93 and 94 of the above described component elements utilized to form pattern F, component elements in the dotted line rectangle 107 will form a modified pattern F'in which perforation 1e is not selected.

On the other hand, the output from AND gate circuit 60 selects perforations 1e and 7e shown in FIG. 7b via OR gate circuits 95 and 96 whereas the output from AND gate circuit 61 selects perforation 7d shown in FIG. 7b via OR gate circuit 96. The output from AND gate circuit 62 selects perforation 70 via OR gate circuit 96 while the output from AND gate circuit 63 selects perforation 7b via OR gate circuit 96. Consequently, AND gate circuits 60 to 64 cooperate to form a signal for pattern E shown in FIG. 7a by combining component elements in rectangle 107 with those in rectangle 108. In this manner, the common utilization of certain circuit elements which are used to generate common parts of different patterns for the groups of 5 elements for synthesizing different patterns, reduces the number of component parts of the pattern signal generating circuit by one-third of the prior pattern signal generating circuit.

FIGS. 8a, 8b and 8c show other examples of patterns which can be displayed using a modified pattern generating sustem embodying the invention. Although in the foregoing embodiment, the component elements used produce common portions of resepctive patterns for synthesizing the different patterns, in this modification, a plurality of groups of elements for synthesizing different patterns are simultaneously driven by a selection signal for forming different patterns. Thus, for example, where groups of elements for synthesizing patterns F and L are selected simultaneously, pattern E shown in FIG. 80 will be formed by the superposition of pattern F on pattern L, shown in FIGS. 8a and 8b, respectively. With this modified embodiment it is possible to form three different patterns by using two' groups of elements for synthesizing patterns. For this reason, it is possible to reduce the number of component parts by one-third of the prior pattern signal generating circuit.

Whilein the above described embodiments the pattern E was formed by adding a portion to pattern F or by superposing on each other the patterns of F and L it is to be understood that the invention is not limited to these particular combinations.

I claim:

1. A pattern generating system for displaying matrix patterns of a character font on a display device including a matrix electrode assembly, and means controlling said assembly comprising a plurality of selectively operable whole pattern character signal generators for displaying different respective whole patterns of less than the total number of characters in said font, a partial 6 pattern signal generator, means for independently driving said whole pattern character signal generators for displaying selected ones of said whole patterns, and means selectively operable for simultaneously driving a selected one of said plurality of whole pattern character signals generators and said partial pattern generator to display a composite modififed generators. including a matrix electrode assembly, and means controlling said assembly comprising a plurality of selectively operable whole respective whole patterns of less than the total number of characters in said font, means for driving a selected one of said plurality of whole pattern character signal generators for displaying a selected whole pattern, and means selectively operable for simultaneously driving a plurality of said whole pattern character signal generators for displaying a composite modified pattern by said matrix electrode assembly by synthesizing different whole patterns of characters in said font not provided by said whole pattern character signal generators individually. pattern by said matrix electrode assembly of characters in said font not provided by said whole pattern character signal generators.

2. A pattern generating system for displaying matrix patterns of a character font on a display device including a matrix electrode assembly, and means controlling said assembly comprising a plurality of selectively operable whole pattern character signal generators for displaying different respective whole patterns of less than the total number of characters in said font, means for driving a selected one of said plurality of whole pattern character signal generators for displaying a selected whole pattern, and means selectively operable for simultaneously driving a plurality of said whole pattern character signal generators for displaying a composite modified pattern by said matrix electrode assembly by synthesizing different whole patterns of characters in said font not provided by said whole pattern character signal generators individually. 

1. A pattern generating system for displaying matrix patterns of a character font on a display device including a matrix electrode assembly, and means controlling said assembly comprising a plurality of selectively operable whole pattern character signal generators for displaying different respective whole patterns of less than the total number of characters in said font, a partial pattern signal generator, means for independently driving said whole pattern character signal generators for displaying selected ones of said whole patterns, and means selectively operable for simultaneously driving a selected one of said plurality of whole pattern character signals generators and said partial pattern generator to display a composite modififed pattern by said matrix electrode assembly of characters in said font not provided by said whole pattern character signal generators.
 2. A pattern generating system for displaying matrix patterns of a character font on a display device including a matrix electrode assembly, and means controlling said assembly comprising a plurality of selectively operable whole pattern character signal generators for displaying different respective whole patterns of less than the total number of characters in said font, means for driving a selected one of said plurality of whole pattern character signal generators for displaying a selected whole pattern, and means selectively operable for simultaneously driving a plurality of said whole pattern character signal generators for displaying a composite modified pattern by said matrix electrode assembly by synthesizing different whole patterns of characters in said font not provided by said whole pattern character signal generators individually. 